Old Single Chip Simple Sample and Hold (For Reference)
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Back to the Sound Lab Project Page This would be a perfect circuit for the Sound Lab because it is simple and relatively low current. After I breadboarded this I sat and played with it for about an hour because it was non-stop fun. The varying patterns and effects had me mesmerized.
Circuit DescriptionHere is how it works. In order to sample and hold we need a sample clock. The sample clock is comprised of U1-A and associated components (R4, R5, C2, R8, C1, R6, R12, R13, R9 and Q2). Current flows through R4 and R5 and charges C2. The voltage on C2 is presented to U1-A's non-inverting input via R8. When the voltage rises above 1/2 +V it causes U1-A's output to go high and turn on Q2 which quickly discharges C2 enough to cause U1-A's output to go low again. This cycle repeats resulting in the sample clock. The sample frequency is adjusted with R4 Sample Rate pot. R6 provides a bit of hysteresis for the comparator and C1 squares up the pulse edges with a shot of positive feedback. The pulse that results at the output of U1-A is about 20 uS wide and goes from -V to +V which is what we need to control the gate of the sample FET Q1.We connect the gate of the sample FET to the pulses via D1. When U1-A's output is low D1 holds the gate at -V which keeps the FET turned off (S and D do no conduct) but when a pulse occurs D1 is reverse biased and Q1's gate is held at ground (via 10K resistor R7) which turns it on (essentially shorting S and D) and allows the voltage on Q1's drain to charge (or discharge) C3 to the voltage at U1-D's output. U1-B is a high impedance buffer with a bit of gain and biasing added by R10, R11, and R16. It provides the output buffering for the sampled and held voltage on C3. C3 will droop slowly but not enough to hear with samples occurring at or above 1 per second or so. U1-D is the input buffer and is biased to 1/2 +V by R2 and R3. Negative going excursions presented to the drain of Q1 cause Q1 to turn on inappropriately so to prevent that we bias U1-D's output to 1/2 +V and then feed the input signal in via R1. The current provided by the input signal causes the voltage at the non-inverting input of U1-D to modulate about the 1/2 +V level. U1-D's output follows this voltage and thus stays above ground unless the input goes very negative. You can change the bias resistors to hold the input even higher if necessary in your application (increase the value of R3). You can also cause the circuit to respond to the input more by increasing the value of both R2 and R3 (proportionally). To provide a trigger pulse output I stretch the sample pulse a bit with U1-C and associated components (D2, C4, and R14). The positive excursion of U1-A's output charges C4 via D2. R14 discharges C4 but the voltage on C4 is above 1/2 +V for about a millisecond or two so you get a pulse wide enough to trigger your envelope generator(s). The TRG OUT signal goes from ground to +V every time the sample clock fires due to D3 which blocks the negative excursions of the output of U1-C. The 2N5457 will most likely work fine as a MPF102 sub and I imagine that any old quad high impedance JFET input op amp will work as well as the TL084. This circuit should work fine up to +/-15V. There you have it, a cool Sample and hold circuit with one chip, a couple of FETs, and a few resistors and capacitors.
Single Chip Simple Sample and Hold Schematic [Schematic PDF]
Single Chip Simple Sample and Hold Parts Layout [Parts Layout PDF]
Single Chip Simple Sample and Hold PC Layout
Connecting the Sample and Hold to the Sound Lab
Single Chip Simple Sample and Hold Parts List
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